Phase locked loop circuits (PLLs) typically receive a predetermined reference frequency and provide a locked output signal having a predetermined multiple of the reference frequency. Generally, a phase detector compares the reference frequency with the output signal after the output signal is divided by the predetermined multiple. The phase detector provides a control signal in response to the comparison. The control signal may then be used by a voltage controlled oscillator (VCO) which provides the output signal and varries the output signal in response to the control signal. A frequency divider for dividing the output signal is coupled between the VCO and phase detector to complete a circuit loop. Such a phase locked loop is disclosed by Ken Burch and Wendell Little in U.S. Pat. No. 4,771,249 entitled "Phase Locked Loop Having A Filter With Controlled Variable Bandwidth" and assigned to the assignee hereof. Burch et al. teach a PLL which uses two filters wherein a first filter has a large bandwidth and the second filer has a mcuh smaller bandwidth. A large bandwidth filter is particularly useful when trying to obtain quick circuit operation at a locked frequency, and a small bandwidth filter is more useful for maintaining stable circuit operation. Burch et al. propose a PLL which uses control circuitry for counting a predetermined number of times the output signal exceeds and falls below a reference frequency before switching from a large bandwidth fiter to a narrow bandwidth filter. Depending upon the control circuitry used, digital pulses may be inadvertently generated resulting in a switch of filters occurring prematurely. Also, in a highly damped PLL system, the output signal may approach the reference signal in a very slow controlled pattern which exceeds the reference frequency only substantially later than when the narrow bandwidth filter is optimally required.